by Jim Venable
7. June 2010 16:03
The SPMT Consortium reached another milestone today. We are pleased to welcome Marvell into the SPMT Promoter group. The promoter group makes up the governing body of the Consortium and is ultimately responsible for approving any specifications released to the members. According to Dr. Sehat Sutardja, chairman, president and CEO of Marvell, he has been investigating serial DRAM for quite some time and believes that Serial Port Memory Technology is the way of the future. I couldn’t agree with him more. When you take a look at the cadre of future memory interface architectures being bandied about in the industry today, nothing comes close to Serial Port Memory Technology in meeting the industry requirements in terms of high bandwidth, low power, low pin count, and low latency. Dr. Sutardja, who is recognized as one of the foremost experts on memory and is also an expert in analog design, says that the future for serial DRAM is now. He stated that the mission is to bring this technology to the industry as a standard. From the beginning, that has been the goal of the SPMT Consortium and we are glad that Marvell along with Samsung, Hynix, LG, ARM, and Silicon Image share the same belief. But, as they say on the 2:00 am infomercials (sometime I suffer from insomnia) " But wait, there’s more!":
We are also announcing a new and very exciting enhancement to the SPMT specification which is available to SPMT Consortium members as of today. We are introducing SerialSwitch technology. This is a game changer. It brings together the best of both worlds into a single memory interface. SerialSwitch enables systems to take advantage of the low power capabilities of parallel memory when low bandwidth is required and when the system demands high performance and high-bandwidth, SerialSwitch technology automatically switches the memory into high bandwidth mode, up to 6.4GB/s, while maintaining the low power benefit of SPMT. Additionally, the architecture allows for plug-in replacement of LPDDR2 memories so that the SoC developer doesn’t have to choose between parallel and serial at the time of the development. Because the SoC is designed for LPDDR2 and SPMT-enabled memory, this gives flexibility to the system designer as well to choose the appropriate memory device, either LPDDR2 or SPMT memory, based on price, availability, and system requirements but using the same SPMT-enabled SoC; as I said, the best of both worlds.
These are exciting times for the Consortium. The response from memory, SoC, and system designers has been incredibly positive. We have been reviewing this enhancement with industry leaders for several months and all say that the technology hits the nail on the head.
If you haven’t had a chance to visit our website to review the technology, I urge you to do so by going to
www.spmt.org
.
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